CURRICULUM VITAE Degree Field University Year Bachelor of

CURRICULUM VITAE
1. Name Surname
Contact Information
Address
: Sezer GÖREN UĞURDAĞ
Phone
Email
2. Birth Date
: 0216 578 2734
: [email protected]
: 02.13.1970
3. Title
: Assoc. Prof.
4. Education
:
Degree
Bachelor of
Science
Master of Science
Doctor of
Philosophy
5.
: Yeditepe University, Faculty of Engineering, Department of Computer
Engineering, A-408, 34755, Ataşehir/İstanbul
Field
Electrical & Electronic
Engineering
Electrical & Electronic
Engineering
Computer Engineering
University
Year
Boğaziçi University
1993
Boğaziçi University
1995
University of California, Santa Cruz,
USA
2003
University
Year
Bahçeşehir University
2005
Yeditepe University
2010
Yeditepe University
2011
Academic Titles
Degree
Assistant
Professor
Assistant
Professor
Associate
Professor
Field
Computer Engineering
Computer Engineering
Computer Engineering
6. Supervised MS Theses & PhD Dissertations
6.1. MS Theses
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Çağatay CURA. Parking Spot Finder: An Automated Software Service with SMS and Map
Interface. 2009.
Ferhat CANBAY. Point Based Correspondenceless Pose Estimation. 2009.
Özgür Özkurt. FPGA Design Security with PUF, Obfuscation, and Partial Reconfiguration.
2012.
Abdullah Yıldız. Fast, Secure, and Remote Multiboot of Low-cost FPGAS. 2012.
Mert Büyükmıhçı. Efficient Video Scalers. (Ongoing)
Cemil Cem Gürsoy. Fault Emulation for Logic Locking. (Ongoing)
Yılmaz Serhan Gener. Fully Random Access Differential LUT. (Ongoing)
Yusuf Türk. (Ongoing)
6.2. PhD Dissertations
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Mehmet Yağmur Gök. Programmable Hardware based Short Read Aligner Using Phred Quality
Scores. 2016. (Co-supervisor)
Ferhat Canbay. Kompleks Dalgacık Dönüşümü Kullanılarak Düşük Güç Tüketimli Yeniden
Yapılandırılabilir Kapı Dizileri İle Doppler Ultrason Sinyallerinin Gerçek Zamanda İşlenmesi.
2016. (Co-supervisor)
Abdullah Yıldız. Synthesis of Multi-core Microcontrollers. (Ongoing)
7. Publications
7.1
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Journals
Canbay F., Levent V.E., Serbes G., Ugurdag H.F., Gören S., Aydin N., "A Code Generator for
Implementing Dual Tree Complex Wavelet Transform on Reconfigurable Architectures for Mobile
Applications," Healthcare Technology Letters (IET), DOI: 10.1049/htl.2016.0034, 2016.
S. Gören, C.C. Gürsoy, A. Yıldız. Speeding Up Logic Locking via Fault Emulation and Dynamic
Multiple Fault Injection. Journal of Electronic Testing, 31(5), Volume 31, pp 525-536, 2015.
B. Yuce, H.F. Ugurdag, S. Gören., G. Dundar. Fast and Efficient Circuit Topologies for Finding
the Maximum of n k-bit Numbers. IEEE Transactions on Computers, 63(8), 1868-81, 2014.
S. Gören, O. Ozkurt, A. Yildiz, H.F. Ugurdag, R.S. Chakraborty, D. Mukhopadhyay. Partial
Bitstream Protection for Low-Cost FPGAs with Physical Unclonable Function, Obfuscation, and
Dynamic Partial Self Reconfiguration. Computers and Electrical Engineering, Elsevier, 39(2),
2013.
S. Gören, H. F. Ugurdag, O. Palaz. Defect-Aware Nanocrossbar Logic Mapping through Matrix
Canonization using Two-Dimensional Radix Sort. ACM Journal of Emerging Technologies in
Computing Systems, 7(3), article 12, 2011.
H.F. Ugurdag, S. Gören, F. Canbay. Gravitational Pose Estimation. Computers and Electrical
Engineering, Elsevier. vol. 36(6), 1165-1180, 2010.
S. Gören. Optimization of Embedded Controllers Based on Redundant Transition Removal and
Fault Simulation Using K-wise Tests. Journal of Circuits, Systems, and Computers, 18(4), 647663. 2009.
S. Gören, A. Karahoca, F. Y. Onat, M.Z. Gören. Prediction of cyclosporine A blood levels: an
application of the adaptive-network-based fuzzy inference system (ANFIS) in assisting drug
therapy. European Journal of Clinical Pharmacology, 64(8), 807-814. 2008.
S. Gören, F. J. Ferguson. On state reduction of incompletely specified finite state machines.
Computers and Electrical Engineering, 33(1), 58-69. 2007.
S. Gören, F. J. Ferguson. Test sequence generation for controller verification and test with high
coverage. ACM Trans. Design Autom. Electr. Syst. 11(4), 916-938. 2006.
7.2 Conference papers
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CC Gursoy, A Yildiz, S Gören, "On optimization of multi-cycle tests for test quality and application
time," 14th IEEE East-West Design & Test Symposium (EWDTS'2016), Yerevan, Armenia, 2016.
M. Buyukmihci, V.E. Levent, A.E. Guzel, O. Ates, M. Tosun, T. Akgun., C. Erbas, S. Gören, H.F.
Ugurdag, "Output Domain Downscaler," International Symposium on Computer and Information
Sciences (ISCIS'2016), Krakow, Poland, 2016.
H.F. Ugurdag, A. Bayram, V.E. Levent, S. Gören, Fast Combinational Circuits for Division by
Small Integer Constants. 23rd IEEE Symposium on Computer Arithmetic, 2016.
F. Canbay, V.E. Levent, G. Serbes, H.F. Ugurdag, S. Gören, N. Aydın, "A Multi-channel Real Time
Implementation of Dual Tree Complex Wavelet Transform in Field Programmable Gate Arrays,"
14th Mediterranean Conference on Medical and Biological Engineering and Computing
(MEDICON'2016),vol. 57, pp 114-118, Cyprus, 2016.
Gener Y.S., Yildiz A., S. Gören, "Low-Cost and Low-Power Video Filtering with Parallel Many
Cores," International Conference on Electrical and Electronics Engineering (ELECO'15), Bursa,
2015.
Canbay F., Levent V.E., Serbes G., Ugurdag, H.F., S. Gören, Aydın N. "An area efficient real time
implementation of dual tree complex wavelet transform in field programmable gate arrays," 15th
IEEE International Conference on Bioinformatics and Bioengineering (BIBE'2015), Belgrade,
Serbia, 2015.
F. Canbay, V.E. Levent, G. Serbes, N. Aydın, S. Gören. Field Programmable Gate Arrays
Implementation of Dual Tree Complex Wavelet Transform. 37th Annual International Conference
of the IEEE Engineering in Medicine and Biology Society (EMBC'2015), Milan, Italy, 2015.
Y. Türk, O. Demir, S. Gören. Real Time Wireless Packet Monitoring with Raspberry Pi Sniffer.
International Symposium on Computer and Information Sciences (ISCIS'2014), Krakow, Poland,
2014.
A. Johnson, S. Saha, R.S. Chakraborty, D. Mukhopadhyay, S. Gören. Fault Attack on AES via
Hardware Trojan Insertion by Dynamic Partial Reconfiguration of FPGA over Ethernet. 9th
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7.3
Workshop on Embedded Systems Security (WESS 2014 (A Workshop of the Embedded Systems
Week (ESWEEK 2014)), New Delhi, India, October 17, 2014.
M.Y. Gök, M.S. Sagiroglu, C. Unsalan, S. Gören. Programmable Hardware based Short Read
Aligner Using Phred Quality Scores. ASE/IEEE International Conference on BioMedical Computing,
Washington DC, USA, 2013.
H.F. Ugurdag, F. Temizkan, S. Gören. Generating Fast Logic Circuits for m-select n-port Round
Robin Arbitration. 21st IFIP/IEEE International Conference on Very Large Scale Integration
(VLSI-SoC), October 2013, İstanbul, Turkey
M.Y. Gök, M.S. Sagiroglu, C. Unsalan, S. Gören. Reconfigurable Hardware-based Genome
Aligner Using Quality Scores. IEEE Signal Processing and Communications Applications
Conference (SIU'2013), North Cyprus, April, 2013.
B. Yuce, H.F. Ugurdag, S. Gören, G. Dundar. A Fast Circuit Topology for Finding the Maximum
of n k-bit Numbers. 21st IEEE Symposium on Computer Arithmetic (ARITH'13), Austin, TX, 2013.
S. Gören, Y. Turk, O. Ozkurt, A. Yildiz, H.F. Ugurdag. Achieving Modular Dynamic Partial
Reconfiguration with Difference-Based Flow. 21st ACM/SIGDA International Symposium on FieldProgrammable Gate Arrays (FPGA'2013), Monterey, CA, 2013.
S. Gören, O. Ozkurt, Y. Turk, A. Yildiz, H.F. Ugurdag. Enabling Difference-Based Dynamic Partial
Self Reconfiguration for Large Differences. IEEE International Design and Test Symposium, Doha,
Qatar, 2012.
H.F. Ugurdag, Basaran A., Akdogan T., Guney V.U., S. Gören. FPGA based Particle Identification
in High Energy Physics Experiments. IEEE International Conference on Application-specific
Systems, Architectures and Processors (ASAP'2012), Delft, Netherlands, 2012.
S. Gören, A. Yildiz, O. Ozkurt, H.F. Ugurdag. FPGA Bitstream Protection with PUFs, Obfuscation
and Multi-boot. International Workshop on Reconfigurable Communication-centric Systems-onChip (ReCoSoC'2011). 2011.
S. Gören, H.F. Ugurdag, and O. Palaz, Defect-Tolerant Logic Mapping for Nanocrossbars Based
on Two-Dimensional Sort, IEEE International Symposium on Computer and Information Sciences.
2010.
S. Gören, H.F. Ugurdag, A. Yildiz, O. Ozkurt. FPGA Design Security with Time Division
Multiplexed PUFs. IEEE International Conference on High Performance Computing & Simulation
(HPCS'2010). 2010.
S. Gören, H.F. Ugurdag, O. Palaz. Defect-Aware Nanocrossbar Logic Mapping using Bipartite
Subgraph Isomorphism & Canonization. IEEE European Test Symposium (ETS’10). 2010.
H.F. Ugurdag, E. Argali, O.E. Eker, A. Basaran, S. Gören, H. Ozcan. Smart Question (sQ): Tool
for Generating Multiple-Choice Test Questions. WSEAS International Conference on Education
and Educational Technology (EDU'09). 2009.
F. Ileri, S. Gören, H.F. Ugurdag, Virtual Smart Board. WSEAS International Conference on
Education and Educational Technology (EDU'09). 2009.
H.F. Ugurdag, S. Gören, F. Canbay. Correspondenceless Pose Estimation from a Single 2D Image
using Classical Mechanics. IEEE International Symposium on Computer and Information
Sciences. 2008.
S. Gören. A Meta-heuristic for Shared BDD Minimization. IFIP/IEEE International Conference on
Very Large Scale Integration (VLSI-SOC). 2008.
S. Gören. Optimization of Interacting Controllers Using K-wise Tests, International Design and
Test Workshop (IDT), 169-174. 2007.
H.F. Uğurdağ, Y. Şahin, O. Başkirt, S. Dedeoğlu, S. Gören, Y.S. Koçak. Population-based FPGA
Solution to Mastermind Game. NASA/ESA Conference on Adaptive Hardware and Systems (AHS),
237-246. 2006.
S. Gören, F.J. Ferguson. Testing Finite State Machines Based On a Structural Coverage Metric.
IEEE International Test Conference (ITC), 773-780. 2002.
S. Gören, F.J. Ferguson. CHESMIN: A Heuristic for State Reduction of Incompletely Specified
Finite State Machines. IEEE/ACM Design Automation and Test in Europe (DATE), 248-254. 2002.
S. Gören, F.J. Ferguson. Checking Sequence Generation for Asynchronous Sequential Elements.
IEEE International Test Conference (ITC), 406-413. 1999.
Pak K. Chan, M.J. Boyd, S. Gören, K. Klenk, V. Kodavati, R. Kundu, M. Margolese, J. Sun, K.
Suzuki, E. Thorne, X. Wang, J. Xu, M. Zhu. Reducing Compilation Time of Zhong's FPGA-Based
SAT Solver. IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), 308309. 1999.
S. Gören, S. Balkir, G. Dündar, E. Anarim. Novel VLSI architectures for morphological filtering.
IEEE Workshop on Nonlinear Image and Signal Processing (NSIP), 875-878. 1995.
National conference papers
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Y. Türk, O. Demir, S. Gören. Dusuk Maliyetli 802.11 Kablosuz Ag Dinleyici. Elektrik- Elektronik,
Bilgisayar ve Biyomedikal Mühendisligi Sempozyumu (ELECO’2014), Bursa, 2014.
F. Canbay, G. Serbes, S. Gören, N. Aydın. Çift-ağaç Karmaşık Dalgacık Dönüşümü’nün Gerçek
Zamanlı Gerçekleştirimi. Otomatik Kontrol Ulusal Toplantısı (TOK’2013), Malatya, 2013.
Basaran, H.F. Ugurdag, T. Akdogan, V.U. Guney, S. Gören, "Ultra-Fast Curve Fitting for Pulses
on FPGA," IEEE Signal Processing and Communications Applications Conference (SIU'2012),
Mugla, Turkey, April 2012.
S. Gören, H.F. Ugurdag, O. Ozkurt, A. Yildiz. PUF, DPSR ve Bulandırma Yoluyla Sayısal
Yongaların Güvenilir Yapılması. EMO 3. Ağ ve Bilgi Güvenliği Ulusal Sempozyumu. 2010.
M. Z. Gören, S. Gören, A. Karahoca, F.Y. Onat. Terapötik İlaç Düzeyi İzlemi Verilerine Veri
Madenciliği Tekniklerinin Uygulanması İle Siklosporin A Kan Düzeylerinin Önceden Tahmini. Türk
Farmakoloji Derneği 19. Ulusal Farmakoloji Kongresi. 341-342. 2007.
S. Gören, S. Balkır, G. Dündar, E. Anarım. Novel VLSI architectures for morphological filtering
(Türkçe). Sinyal İşleme ve Uygulamaları Kurultayı (SIU), A: Görüntü İşleme. 187-192. 1995.
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7.4 Other publications
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Y. S. Gener, A. Yildiz, S. Gören. Low-Cost and Low-Power Video Filtering with Parallella,
https://parallella.org/forums/viewtopic.php?f=53&t=2522&sid=3261c3236c402e9782866a93e
89e4ad8&p=14343#p14330, 2015.
S. Gören. Hardware Implementation of Advanced Morphological Filters. Technical Report. Centre
de Morphologie Mathematique, Ecole des Mines, Paris, Fransa, 1996.
S. Gören. HDL Tool Kit. Technical Report. SCTest, Baskin School of Engineering, University of
California, Santa Cruz. 2006.
S. Gören, Abdullah Yıldız, Onur Demir. OMAPL138 Experimenter Kit Lab Manual. 2011.
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8. Projects
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Pricipal Investigator – Sayısal Yonga Çoklu-Darbeli Üretim Testleri İçin Hata Emülasyonu
Yönteminin Geliştirilmesi. Tübitak 114E022 no’lu proje. 2014-halen.
Consultant – Savaş Sistemleri için Gömülü Sistemli Uyarlama Birimi. Tübitak 1511 nolu Öncelikli
Alanlar Araştırma Teknoloji Geliştirme ve Yenilik Projeleri Destekleme Programı. Vestel Savunma.
2013-2014.
Researcher–Hdl Tool Kit. TÜBİTAK Doktora sonrası Araştırma Bursu. University of California,
Santa Cruz, CA, ABD. 2006.
Lead Engineer (Design Verification) –Design Verification and FPGA prototyping of fabric based
storage application processing chip at wire speeds ranging from 1Gb to 10Gbps across multiprotocol storage networks. Aarohi Communications (Emulex), San Jose, CA, ABD. 2002-2004.
Lead Engineer (Design Verification) –System level design verification of network packet processor
chip. PMC-Sierra, San Jose, CA, ABD. 2001-2002.
Researcher (Software Testing) –Software Test of TestBuilder -High Level Design Verification Tool.
Cadence, San Jose, CA, ABD. 1999-2000.
Researcher (Software Testing) –Software Test of SignalScan -Waveform Viewer Tool Software.
Cadence, San Jose, CA, ABD, 1999.
Researcher–Checking Sequence Generation for Flip-flops and Latches. MICRO Projesi, University
of California Santa Cruz, ABD, 1999.
Researcher –Hardware Implementation of Advanced Morphological Filters. TÜBİTAK NATO-A2.
Centre de Morphologie Mathematique, Ecole des Mines, Paris, Fransa, 1996.
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9. Awards
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National Education Ministry PhD Award
TUBITAK NATO A2 Research Award
Placed 44th in University Entrance Exam
Placed 5th in Science High School Entrance Exam
10. Administrative Duties
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Department Head, Computer Engineering (2016-ongoing)
Member of Engineering Faculty Board of Directors (2014-ongoing)
11. Memberships
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ACM member
IEEE member
IEEE Test Technology Technical Council member
Program committee member, IEEE NASA/ESA Conference on Adaptive Hardware and Systems
(AHS), 2014
Program committee member, IEEE NASA/ESA Conference on Adaptive Hardware and Systems
(AHS), 2013
Program committee member, IEEE NASA/ESA Conference on Adaptive Hardware and Systems
(AHS), 2012
Program committee member, IEEE NASA/ESA Conference on Adaptive Hardware and Systems
(AHS), 2011
Program committee member, IEEE NASA/ESA Conference on Adaptive Hardware and Systems
(AHS), 2006
Organizing committee member, The 21st IFIP/IEEE International Conference on Very Large
Scale Integration (VLSI-SOC), 2013
Program committee member, IEEE Signal Processing and Communications Applications
Conference (SIU), 2014
Program committee member, IEEE Signal Processing and Communications Applications
Conference (SIU), 2013
Program committee member, IEEE Signal Processing and Communications Applications
Conference (SIU), 2012
Program committee member, IEEE International Design and Test Symposium, 2014
Program committee member, IEEE International Design and Test Symposium, 2013
Program committee member, IEEE International Design and Test Symposium, 2012
Program committee member, Intl. Symposium on Computer and Information Sciences (ISCIS),
2012
Organizing committee member, 2011 International Conference on High Performance Computing
& Simulation (HPCS), 2011
Organizing committee member, International Wireless Communications and Mobile Computing
Conference (IWCMC), 2011
Program committee member, Intl. Symposium on Computer and Information Sciences (ISCIS),
2011
Program committee member, IEEE Intl. Conference on Design and Technology (IDT), 2010
Program committee member, Yıldız Teknik Üniversitesi Yıldızlı Projeler Yarışması, 2010
Program committee member, Intl. Symposium on Computer and Information Sciences (ISCIS),
2010
Program committee member, IEEE Intl. Conference on Design and Technology (IDT), 2009
Program committee member, IEEE Intl. Design and Test Workshop (IDT), 2007
Reviewer, TÜBİTAK-TEYDEB
Panellist, TÜBİTAK Elektrik Elektronik ve Enformatik Araştırma Grubu (EEEAG), 2014
Panellist, TÜBİTAK Elektrik Elektronik ve Enformatik Araştırma Grubu (EEEAG), 2013
Panellist, TÜBİTAK Elektrik Elektronik ve Enformatik Araştırma Grubu (EEEAG), 2009
Reviewer, ICCAD
Reviewer, European Test Symposium
Reviewer, Elsevier Computers and Electrical Engineering
Reviewer, Elsevier Digital Signal Processing
Reviewer, IET Computers and Digital Techniques
Reviewer, IEEE Trans. On Computers
Reviewer, ACM JETC
Reviewer, IEEE Embedded Systems Letters
Reviewer, Computer Journal
Reviewer, IET Computers & Digital Techniques
Reviewer, MICRO program of California State, 2001-2003
12. Taught courses in last two years
Academic
Year
Semester
Fall
2014-2015
Spring
Fall
2013-2014
Spring
Course Name
Weekly Hour
Lec.
Lab.
Student
Count
CSE421 Microprocessors &
Microcontrollers
2
2
12
CSE222 Intro. Digital
Electronics
2
2
40
CSE526 Reconfigurable
Computing
3
0
10
CSE326 Embedded Systems
Programming
3
0
25
2
2
27
2
2
20
CSE538 Real-Time Sytems
3
0
10
CSE222 Intro. Digital
Electronics
2
2
30
2
2
10
3
0
22
CSE222 Intro. Digital
Electronics
CSE421 Microprocessors &
Microcontrollers
CSE421 Microprocessors &
Microcontrollers
CSE326 Embedded Systems
Programming